1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and more specifically to a method for forming a stacked structure capacitor in a semiconductor device.
2. Description of Related Art
In semiconductor memories, particularly in a DRAM (dynamic random access memory), the most important problem is to increase an integration density or the number of elements per chip. In the DRAM memory, the simplest memory cell consists of one transfer transistor and one capacitor (one transistor type memory cell), and is widely used since it is the most suitable for increasing the integration density.
However, increase of the integration density results in reduction of the memory cell size, so that the capacitance of the capacitor is correspondingly inevitably reduced. Reduction of the capacitance leads to a drop of S/N ratio (signal to noise ratio), which often causes malfunction of the DRAM. Namely, this has become a large problem in an advanced micro-fabrication.
Under this circumstance, one method has been proposed, which has attempted to increase the capacitance of the capacitor under the same occupying area, by causing the capacitor plate surface to have convexities and concavities so as to increase an effective surface area of the capacitor plate.
As one process for this method, Japanese Patent Application Laid-open Publication No. JP-A-5-291523 has proposed to roughen the capacitor plate surface by use of an ion implantation process.
Now, the prior art process disclosed in JP-A-5-291523 will be described with reference to FIGS. 1A to 1F, which are diagrammatic sectional views for illustrating the prior art process for forming a so called stacked structure capacitor in a semiconductor device.
Referring to FIG. 1A, for a device isolation, a field oxide film 102 having a thickness on the order of 500 nm is selectively formed on a principal surface of a silicon substrate 101 of, for example, P-type, by utilizing a LOCOS (local oxidation of silicon) process. A gate oxide film 103 is formed an the principal surface of the silicon substrate 101, and a patterned gate electrode 104 having a thickness on the order of 300 nm is on format the gate oxide film 103. Then, an insulating film is deposited to cover the whole surface by a known CVD (chemical vapor deposition) process, and an anisotropic dry etching is conducted on the deposited insulating film to form a sidewall 105 which covers each side surface of each gate electrode 104. Furthermore, for example, arsenic ions are implanted using, as a masks each data electrode 104 having each side surface covered with the sidewall 105, and a heat treatment is conducted. Thus, a pair of source/drain diffused regions 106 are formed in a principal surface region of the silicon substrate 101 at opposite sides of each gate electrode 104, respectively, as shown in FIG. 1A.
Referring to FIG. 1B, a first interlayer insulator film 107 having a thickness on the order of 400 nm is formed to cover the whole surface by the CVD process, and a contact hole 108 is formed to penetrate through the interlayer insulator film 107 to reach one source/drain region of each pair of source/drain regions 106, by use of a conventional lithography and a dry etching technology. A polysilicon film 109 having a thickness on the order of 200 nm is deposited by the CVD process to fill the contact hole 108 and to cover the first interlayer insulator film 107. Succeedingly, arsenic is ion-implanted to the polysilicon film 109 with a dose of 5.times.10.sup.15 ion/cm.sup.2 and an accelerating energy of 50 KeV, and a heat treatment is carried out at a temperature of 900.degree. C. in an N.sub.2 atmosphere. Thus, a structure as shown in FIG. 1B is obtained.
Thereafter, as shown in FIG. 1C, N.sup.- (nitrogen) ions 110 are implanted into the polysilicon film 109 with a dose of 5.times.10.sup.17 ion/cm.sup.2 and an accelerating energy of 20 KeV, so as to modify the property of a surface of the polysilicon film 109 into a silicon nitride (Si.sub.X N.sub.Y) 111, as shown in FIG. 1C. The silicon nitride 111 is removed by a wet etching using a phosphoric acid (H.sub.3 PO.sub.4) aqueous solution. Thus, the polysilicon film 109 has a roughened surface 109A having convexities and concavities as shown in FIG. 1D.
Then, the polysilicon film 109 having the roughened surface 109A is patterned by use of a conventional lithography and a dry etching technology, so that a capacitor lower plate 112 is formed as shown in FIG. 1E.
A capacitor dielectric film 113 formed of Si.sub.3 N.sub.4 is deposited to cover a surface of the capacitor lower plate 112 by use of a low pressure CVD process, and furthermore, for a capacitor cell plate, a polysilicon film having a thickness on the order of 300 nm is deposited to cover the dielectric film 113 by the CVD process, and phosphorus is doped to the deposited polysilicon film by a thermal diffusion using a source of POCl.sub.3. Furthermore, the phosphorus-doped polysilicon film is patterned by use of the lithography and the dry etching technology, so that a capacitor upper plate 114 is formed as shown in FIG. 1F.
Thereafter, a second interlayer insulator film, a contact hole, a bit line and a covering film (all of which are not shown in the drawing) are formed. Thus, a memory cell is completed.
As mentioned above, the prior art process disclosed in JP-A-5-291523 is characterized in that, the N.sup.+ ions are implanted into the polysilicon film which will become the capacitor lower plate, to modify the property of the surface of tie polysilicon film into the silicon nitride, and then, the silicon nitride is etch-removed, with the result that the capacitor lower plate has the roughened surface. However, in order to nitride the polysilicon film surface by the N.sup.+ ions, the N.sup.+ ion implantation requires a high dose of not less than 5.times.10.sup.17 ion/cm.sup.2. However, the ion implantation of such a high dose needs a long time.
For example, assuming to use an existing high-current ion implantation equipment which can process 17 wafers in each batch and to execute the ion implantation with a beam current of 20 mA, about 5 hours are required for each one batch. This greatly lowers the production efficiency of a semiconductor device mass production.
Furthermore, with the surface modification obtained by using the ion beam, a degree of roughness at a boundary between the modified surface layer and an unmodified underlying layer is on the level of atoms. Accordingly, the convexities and concavities of the capacitor lower plate surface obtained by etch-removing the modified surface layer are not so large. As a result, an effective surface area of the modified surface increases to only about 1.2 times at maximum, as compared with the unmodified surface.
Other than the above mentioned method, in order to increase the capacitance of the capacitor, various methods of changing the plate structure have been proposed. For example, a cylinder type and a multi-fin type are known. These structures can substantially increase the capacitance without changing the occupying area, although they have such a disadvantage that the height inevitably becomes high. If these structures are adopted, the cylinder type can increase the capacitance to about 1.9 times, and the multi-fin type can increase the capacitance to about 2 times in case that two fins are provided.
Accordingly, in the stacked structure capacitor manufactured by the prior art method using the ion beam, the rate of increase of capacitance in the stacked structure capacitor is small aid not satisfactory in comparison with the just above mentioned capacitors of the cylinder type and the multi-fin type.